iCEBreaker FPGA: VGA Pong Demo

An ICEBreaker FPGA development board with an attached VGA cable

Through a university course I got in contact with iCEBreaker FPGA development boards. These boards contain a tiny Lattice FPGA, are relatively cheap to get (especially considering the price of other “big” FPGA boards) and are really easy to get started with. We used open source tools for synthesis and simulation of the Verilog designs. The tools performed really well and were very lightweight in comparison to their commercial counterparts. As a final project of the course, I created this little Pong game which is displayed on a standard VGA monitor.

Video of Pong game

I chose an old-school VGA output because the signaling is really trivial. Three analog RGB channels, two digital sync pulses for vertical and horizontal synchronization. I chose the “standard” 640 x 480 VGA resolution, because then the required pixel clock of 25.175 MHz would be easily achievable with the FPGA’s internal PLL.

principle of how VGA timing corresponds to the screen area

Because the FPGA does not have enough RAM for a complete (color) framebuffer, I use the vertical and horizontal counters of the VGA scanning to “dynamically” create the image on the fly. This is fairly easy since I only use rectangular shapes, but it allows me to have the full color range available without sacrificing resolution.

diagram of the FPGA design

This was my first contact with Verilog and I learned a lot from it.